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Predictable Resource Sharing on Multi-Core Platforms
chair:Chair of Micro Hardware Technologies for Automation
type:Masterarbeit/Diplomarbeit
time:01.01.2012
place:

Building 40.28, KIT

person in charge:Dr. Jian-Jia Chen
links:Download PDF

The on-going trend towards multi-core platforms for embedded systems fulfills the need of increased computation performance. MPSoCs normally contain shared resources in order to satisfy cost constraints. However, such development sacrifices timing predictability, which is required for real-time systems. Therefore, recent research in the area of real-time systems has focused on the problem of analyzing the performance of such systems. If tasks executed on processing elements access the shared resource simultaneously, a request can be delayed due to resource access contention. This increases the worst-case access time compared to single processor architectures and consequently, the worst-case response time (WCRT) of each task. It is important to determine this WCRT in order to guarantee the correct functionality of real-time systems with deadline satisfaction. This affects embedded systems in general and ard real-time systems in particular -- where the completion of a task after its deadline can result in critical failure. Examples for such systems are control systems for the automotive or avionic industry.


We have proposed several approaches to analyze the behavior with one shared resource (e.g., shared memory). This thesis will focuses on the topic of analyzing the timing behavior of multi-core systems with multiple shared resources. Adding more shared resources to the system has several consequences that reduce the analyzability of the system and accordingly, the timing predictability.  As a result, finding a WCRT is more complicated. This thesis proposal will focus on the analysis of two processing elements (two cores) in order to describe the fundamental problems of deriving a tight upper bound of the completion time. The thesis will be based on the tools that have been developed in Matlab. 

The workload will be

  • 40%: analysis
  • 40%: implementation
  • 20%: evaluations

 

Any further queries or clarifications can be directed to Dr. Jian-Jia Chen (119 in Bldg. 40.28).  If you have an interest in our research activities just drop by our offices for coffee and discussion.
 

Tricore Systems (Infineon AG)Intel SCC