Because of the non-volatile, shock-resistant, and power-economic characteristics, flash memory is widely adopted in various storage systems, especially for embedded systems. However, its high bit error rate and low endurance also introduce serious challenges on the reliability issue. These problems are further exacerbated when high-density flash memory is adopted. Typically, data errors are corrected by error correction codes (ECCs) although they are less capable in the handling of burst data errors.  When a cell is worn out, the cell cannot be used to provide reliable storage any more. Traditional reliability management relies on wear-leveling mechanisms to decide which block to store a page. Such an abstraction reduces the overhead of management. However, it also introduces pessimism for managing the flash memory.

This thesis will utilize the information provided from the hardware. The objective is to improve the reliability, e.g., lifetime, error rate satisfaction, etc., of flash memory.  The tasks are as follows: (1) evaluate and formulate the error bit distribution when a flash memory is adopted, (2) develop a mechanism for enhancing the reliability based on the error bit distributions, and (3) evaluate the impact by experiments.  The fundamental knowledge to program with C or C++ is assumed. The tasks can be broken down as follows:

• 20%: analysis
• 60%: implementations
• 20%: evaluations

This thesis will also involve Dr. Yuan-Hao Chang from Academia Sinica in Taiwan.  Any further queries or clarifications can be directed to Dr. Jian-Jia Chen.